1. Field of the Invention
This invention relates to a method of fabricating a dynamic random access memory (DRAM) device, and more particularly to a method of fabricating a DRAM device for reducing the stress between a top electrode of a DRAM capacitor and an interlevel dielectric layer.
2. Description of Related Art
The main purpose of the capacitor in a DRAM device is to save logical data. The capacity in a DRAM device must be large enough, so the data access time can be fast. When the device size scales down, the capacity decreases. It is typical to use a high-k dielectric material for DRAM capacitors. Using the high-k dielectric can increase the capacity in the same thickness of dielectric.
The semiconductor structure configuration of a high-k dielectric material for a conventional DRAM device memory cell unit is shown in the cross-sectional schematic view in FIG. 1. A field oxide layer 11, polygate layer 13, source/drain regions 12 and word line 14 of a MOS transistor 15 are formed over the surface of a silicon substrate 10. After the formation of the transistor 15, an oxide layer 16 is deposited over the surface of the substrate 10. Contact openings 17 are formed at designed locations above the source/drain regions 12 by etching. The contact openings 17 are then filled with a conductive material, such as tungsten, to form plugs 18. A conductive layer 19, such as a heavily doped polysilicon layer, is deposited over the plugs 18 to form a bottom electrode of the capacitor. A dielectric layer 20, such as a tantalum oxide (Ta.sub.2 O.sub.5) layer, is deposited on the top of the conductive layer 19 and oxide layer 16. A titanium nitride layer 21 is deposited over the dielectric layer 20 to form a top electrode of the capacitor. Then, an interlevel dielectric layer 22, such as a borophosphosilicon glass (BPSG) layer, is formed over the titanium nitride layer 21 to complete the fabrication of the conventional DRAM device.
The titanium nitride layer 21 is used as the top electrode of the DRAM capacitor, while the dielectric layer is a high-k dielectric layer in the above DRAM device. The stress between titanium nitride layer 21 and interlevel dielectric layer 22 of the DRAM capacitor will increase when the temperature is above 600.degree. C. This will cause interlevel dielectric layer 22 to crack, thus increasing leakage current during the following BPSG reflow for planarization.
Thus, to reduce the stress between titanium nitride layer 21 and interlevel dielectric layer 22 and to decrease the crack and the leakage current, a polysilicon layer is formed between the titanium nitride layer 21 and the interlevel dielectric layer 22 to overcome the above problems. Another semiconductor structure configuration of a high-k dielectric material for a conventional DRAM device memory cell unit is shown in the cross-sectional schematic view in FIG. 2. A field oxide layer 31, polygate layer 33, source/drain regions 32 and word line 34 of the MOS transistor 35 are formed over the surface of a silicon substrate 30. After the formation of the transistor 35, an oxide layer 36 is deposited over the surface of the substrate 30. Contact openings 37 are formed at designed locations above the source/drain regions 32 by etching. The contact openings 37 are then filled with a conductive material, such as tungsten, to form plugs 38. A conductive layer 39, such as a heavily doped polysilicon layer, is deposited over the plugs 38, and forms a bottom electrode of the capacitor. A dielectric layer 40, such as a tantalum oxide layer, is deposited on the top of the conductive layer 39 and oxide layer 36. A titanium nitride layer 41 is deposited over the dielectric layer 40 to form a top electrode of the capacitor. Then, a polysilicon layer 42 is deposited over the titanium nitride layer 41. An interlevel dielectric layer 43, such as a borophosphosilicon glass layer, is formed over the titanium nitride layer 41 to complete the fabrication of this conventional DRAM device.
The known methods to form a polysilicon layer between the titanium nitride layer and the interlevel dielectric layer make the fabrication more complex and expensive, though it does reduce crack formation and leakage current.